The present invention relates to a method of fabricating a lateral bipolar transistor in a CSAG (CMOS self-aligned gate) process.
In modern integrated circuit design there is an increasing need to integrate analog and digital functions on the same chip. Because of the densities possible metal oxide semiconductor processes are the ones most commonly used for this purpose although some analog functions still require bipolar transistors to achieve required performances. Examples of the foregoing are high temperature voltage references and high temperature current references. It is possible in the present state of the art to integrate bipolar transistors into a complementary metal oxide process but parasitic leakage toward the substrate degrades the intrinsic characteristics of the transistor and might be dangerous for other circuits resident on the same substrate.
A standard CSAG process integrates a lateral PNP (or NPN) transistor by using an N-tank (or P-tank) diffusion as base and two adjacent P+ (or N+) diffusions to form the emitter and collector. A polysilicon layer is used to define the distance between the emitter and collector. In such a structure together with the desired bipolar lateral transistor there are two additional parasitic transistors formed. One is a MOS transistor whose source is the emitter, whose gate is the polysilicon layer and whose drain is the collector. The second parasitic transistor is the bipolar transistor which has as its emitter the emitter of the lateral transistor, as its base the base of the lateral transistor and as its collector the substrate. The usual way to avoid the effects of the parasitic MOS transistor is to connect together the polysilicon layer with the diffused emitter region. Since the emitter is normally biased in magnitude at the highest potential, the gate of the p-channel or N-channel MOS transistor will be at the same potential so that the transistor will always be off.
The effect of the bipolar parasitic transistor is to generate a leakage to the substrate which reduces the efficiency of the bipolar lateral transistor as well as being a potential problem for other circuits resident on the same substrate.
Accordingly, it is the principal object to provide an improved bipolar transistor in an MOS or CMOS process. It is a further object to provide a bipolar transistor in a MOS or CMOS process having a minimal emitter to substrate leakage.